552AD000104DG【PDF 6/15 页】OSCILL 155.52/156.25MHZ VCXO SMD

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Si5 52

Table 5. CLK± Output Phase Jitter (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Phase Jitter (RMS) 1,2,5

? J

Kv = 33 ppm/V

ps

for F OUT 10 to 160 MHz

CMOS Output Only

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

—

0.63

0.62

—

—

Kv = 45 ppm/V

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

—

—

—

—

—

—

—

—

—

0.63

0.62

0.67

0.66

0.74

0.72

0.83

0.8

1.26

1.2

—

—

—

—

—

—

—

—

—

—

ps

ps

ps

ps

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with V C =1.65V, V DD =3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for F OUT > 250 MHz, 20 MHz for 50 MHz < F OUT <250 MHz,

2 MHz for 10 MHz < F OUT <50 MHz.

Table 6. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

J PER

Test Condition

RMS

Peak-to-Peak

Min

—

—

Typ

2

14

Max

—

—

Units

ps

ps

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

6

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